As it is well known, a metal wiring is required to apply an electric signal to a semiconductor device, and a metal wiring process having a multi-layer metal structure of at least two metals is currently used for manufacturing a highly integrated semiconductor device. Such a conventional metal wiring process is described in detail with reference to FIGS. 1A to 1G.
FIGS. 1A to 1G are cross-section views showing a method for manufacturing a conventional semiconductor device.
At first, referring to FIG. 1A, a first metal layer 2 is formed by performing a coating process such as a spin coating to apply an electric signal to a semiconductor device (not shown) formed on a semiconductor substrate. Thereafter, an interlayer insulating layer 4 is formed on the first metal layer 2, and the interlayer insulating layer 4 is planarized by applying a chemical mechanical polishing (CMP) process to the formed interlayer insulating layer 4.
In the next step, as shown in FIG. 1B, a photoresist layer is coated on a top of the interlayer insulating layer 4, and a first photoresist layer pattern 6 is formed by selectively removing a portion of the photoresist layer to a predetermined depth by using a pattern mask. A via hole 8, as shown in FIG. 1C, is then formed by etching the interlayer insulating layer 4 using the formed first photoresist layer pattern 6 as a mask. In sequence, the remained first photoresist layer pattern 6 is removed by performing a streaming process.
In the following step, as shown in FIG. 1D, a barrier metal 10 is deposited on top of the interlayer insulating layer 4a having the via hole 8 formed thereon and the first metal layer 2. In addition, a second metal layer 12 is coated on a top of the deposited barrier metal 10 by performing sputtering processes.
Sequentially, by applying, as shown in FIG. 1E, a CMP or an etch-back process to the deposited barrier metal 10 and the coated second metal layer 12, the deposited barrier metal 10 and the coated second metal layer 12 are planarized so as to form a barrier metal 10a and a second metal 12a. 
Thereafter, by performing a sputtering process on the surfaces comprising the tops of the interlayer insulating layer 4a, the barrier metal 10a and the second metal 12a, as shown in FIG. 1F, a third metal layer 14 is formed. A photoresist layer is then coated on a top of the third metal layer 14 and a second photoresist layer pattern 16 is formed by patterning the photoresist layer.
Finally, a third metal layer pattern 14a is formed by dry etching the third metal layer 14, wherein the second photoresist layer pattern 16 is utilized as a mask, as shown in FIG. 1G. Accordingly, the first metal layer 2 and the third metal layer pattern 14a are electrically connected by the barrier metal 10a and the second metal 12a. 
However, a method for forming a metal wiring of a conventional semiconductor device described above is formed by a previously defined process, and therefore, more fabrication installations are required for foundry companies to manufacture devices capable of operating at a voltage desired by a customer.
Furthermore, because a metal layer is formed in a multi-layer structure to form a metal wiring of the semiconductor device useful at a high voltage, there is an increased probability of generating an error as the number of metal layers increases.